The present invention relates generally to integrated circuit (IC) designs, and more particularly to a method and system used for creating a power-on reset signal.
A power-on reset device (POR) is commonly found in today's integrated circuit designs and is used to perform many different tasks. As an example, the power-on reset device may first be tasked to ensure that the processor starts at a known address when power is first applied to an integrated circuit. To accomplish that task, the POR logic output holds the processor in its reset state when the processor's power supply is first turned on. The POR's second task is then to keep the processor from starting its operation from that known address until certain events have occurred. For example, three events may be required to happen: the system power supplies have stabilized at the appropriate levels; one or more processor's clocks have settled; and the internal registers have been properly loaded. The POR accomplishes this second task through an onboard timer, which continues to hold the processor in its reset state for a prescribed period of time. That timer triggers after the processor's power supply reaches a specific voltage threshold. After a set time elapses, the timer expires, causing the POR output to become inactive, which in turn makes the processor come out of reset to begin operation. The processor's data sheet specifies the required duration of the timer's delay. The timer, incidentally, is the functional element that differentiates a POR from a voltage detector, a device that also detects a voltage threshold, but does not time an event.
However, conventional power-on reset circuit devices use resistance and capacitance (RC) components to generate the power-on reset signal. While these RC components provide an RC characteristic that can be used to determine the duration of the reset, they are not easily controlled. Even if a proper control mechanism is installed, the mechanism is often very cost prohibitive in today's integrated circuit designs.
It is therefore desirable to devise a method and system for performing an all-digital power-on reset.